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E2B0026-27-Y2
Semiconductor MSM6779
Semiconductor 160-DOT SEGMENT DRIVER (TCP)
This version: Nov. 1997 MSM6779 Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM6779 is a LCD dot matrix segment driver. Fabricated in CMOS technology, the device consists of 160-bit latches I and II, a 160-bit level shifter, and a 4-level driver. The MSM6779 latches the 4-bit parallel display data sent from a microcontroller or a LCD controller to generate a LCD driving signal. This MSM6779 has a power-save function that sets all the drivers except one to the low supply current status (IDD SBY). This driver's 3V-operation allows significant reduction in current consumption, suitable for battery-driving. The bias voltage to specify a drive level can be supplied externally. The MSM6779 can be used for various types of LCD panels.
FEATURES
* Logic supply voltage : 2.7 V to 5.5 V * LCD drive voltage : A wide range from 14 V to 28 V * Applicable LCD duty : 1/64 to 1/256 * The bias voltage can be supplied externally. * LCD outputs : 160 * A power-save function to reduce power consumption in a large-screen LCD panel. * A 4-bit parallel data transfer to reduces its transfer speed to 1/4 of conventional serial transfer, providing low power consumption. * Data transfer clock frequency : 6.5 MHz (VDD=4.5 V) 4.0 MHz (VDD=2.7 V) * 35mm-wide-film TCP Tin-plating User area : 8 mm
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MSM6779
BLOCK DIAGRAM
O1 O2 O3 O158 O159 O160
V1L V3L V4L VEEL
160-DOT 4-LEVEL DRIVER VDD VEE
V1R V3R V4R VEER
DF DISPOFF
160-bit LEVEL SHIFTER
VDD VSS
LOAD
160-bit LATCH (II)
D0 D1 D2 D3
DATA CONTROL
160-bit LATCH (I) (4X40)
SHL
20-bit SHIFT REGISTER
CP EIO1
CONTROL CIRCUIT
EIO2
VDD VSS
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PIN CONFIGURATION (TOP VIEW)
O160 O159 O158 V1R V3R V4R VEER VDDR SHL VSS EIO2 D0 D1 D2 D3 CP LOAD DF DISPOFF EIO1 VDDL VEEL V4L V3L V1L
O3 O2 O1
Note: The drawing shown does not specify the exact outline of the TCP; it only specifies the pin layout.
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VDD-VEE*1 VI TSTG Condition Ta=25C Ta=25C Ta=25C -- Rating -0.3 to 6.5 0 to 30 -0.3 to VDD+0.3 -30 to +85 Unit V V V C
*1 V1>V3>V4>VEE, VDDV1>V3VDD-10 V, VEE+10 VV4>VEE V1=V1L=V1R, V3=V3L=V3R, V4=V4L=V4R, VEE=VEEL=VEER
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (1) Supply Voltage (2) Operating Temperature Symbol VDD VDD-VEE*1 Top Condition -- -- -- Range 2.7 to 5.5 14 to 28 -20 to +75 Unit V V C
*1 V1>V3>V4>VEE, VDDV1>V3VDD-7 V, VEE+7 VV4>VEE V1=V1L=V1R, V3=V3L=V3R, V4=V4L=V4R, VEE=VEEL=VEER Note: Unlike mold packages, TCP has a low light resistance. Therefore, they are protected from light.
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD=2.7 V to 5.5 V, Ta=-20 to +75C) Parameter "H" level Input Voltage "L" level Input Voltage "H" level Input Current "L" level Input Current "H" level output Voltage "L" level output Voltage ON Resistance Symbol VIH VIL IIH IIL VOH VOL RON Condition --*1 --*1 VI=VDD, VDD=5.5 V *1 VI=0 V, VDD=5.5 V *1 IO=-0.2 mA, VDD=2.7 V *2 IO=0.2 mA, VDD=2.7 V *2 VDD-VEE=25 V, VDD=2.7 V, Stand-by Current Consumption IDD SBY IDD I VN-VO I=0.25 V *3 *4 fCP=4.0 MHz, VDD=3.0 V VDD-VEE=25 V, No load *5 fCP=4.0 MHz, VDD=3.0 V VDD-VEE=25 V, No load *6 Current Consumption (2) IEE fCP=4.0 MHz, VDD=3.0 V VDD-VEE=25 V, No load *7 Current Consumption (3) IV fCP=4.0 MHz, VDD=3.0 V VDD-VEE=25 V, No load *8 Input Capacitance CI f=1 MHz -- 5 -- pF -- -- 200 mA -- -- 2.0 mA -- -- 1.5 mA -- -- 300 mA Min. 0.8 VDD -- -- -- VDD-0.4 -- -- Typ. -- -- -- -- -- -- 1.5 Max. -- 0.2 VDD 1 -1 -- 0.4 3.0 Unit V V mA mA V V kW
Current Consumption (1)
Applicable to LOAD, CP, D0~D3, EIO1, EIO2, SHL, DF, DISPOFF pins Applicable to EIO1, EIO2 pins VN=VDD-VEE, V4=14/16 (VDD-VEE), V3=2/16 (VDD-VEE), VDD=V1 Applicable to O1~O160 pins Display data 1010.....fDF = 45 Hz, Current from VDD to VSS when the display data is not fetching. *6 Display data 1010.....fDF = 45 Hz, Current from VDD to VSS when the display data is fetching. *7 Display data 1010.....fDF = 45 Hz, Current from VDD to VEE *8 Display data 1010.....fDF = 45 Hz, Current on V1, V3, and V4 pins. *1 *2 *3 *4 *5 V1=VIL=VIR, V3=V3L=V3R, V4=V4L=V4R, VEE=VEEL=VEER Note: The above values are quaranteed when TCP is protected from light.
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Semiconductor Switching Characteristics
MSM6779
(2.7VDD<4.5 V, Ta=-20 to +75C) Parameter Clock Frequency Clock Pulse Width Load Pulse Width Clock Pulse Rise/Fall Time Data Set-up Time Data Hold Time Clock Load Time 1 Clock Load Time 2 Load Clock Time 1 Load Clock Time 2 Propagation Delay Time EIO1, EIO2 Set-up Time EIO1, EIO2 Hold Time Symbol fCP tW1 tW2 tr, tf tDSU tDHD tCL1 tCL2 tLC1 tLC2 tPHL tESU tEHD CL=15 pF -- -- Condition DUTY=50%, VDD=2.7 V -- -- -- -- -- -- -- -- -- Min. -- 90 110 -- 80 65 0 100 100 100 -- 80 80 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 4.0 -- -- 20 -- -- -- -- -- -- 380 -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns
Note: The above values are quaranteed when TCP is protected from light.
tf tW1 CP 0.8 VDD 0.8 VDD 0.2 VDD tDSU D0~D3 0.8 VDD 0.2 VDD tCL1 LOAD 0.2 VDD tW2 tr tf tLC2 tCL2 0.8 VDD 0.8 VDD 0.2 VDD tLC1 tDHD tW1 tr tW1 0.8 VDD 0.2 VDD 0.8 VDD
0.8 VDD CP 1 LOAD tPHL EIO1, EIO2 (Output) 0.2 VDD EIO1, EIO2 (Input) 0.2 VDD tESU tEHD 0.2 VDD 2 38 0.2VDD 39 40 0.2 VDD 41
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Semiconductor Switching Characteristics
MSM6779
(4.5VDD5.5 V, Ta=-20 to +75C) Parameter Clock Frequency Clock Pulse Width Load Pulse Width Clock Pulse Rise/Fall Time Data Set-up Time Data Hold Time Clock Load Time 1 Clock Load Time 2 Load Clock Time 1 Load Clock Time 2 Propagation Delay Time EIO1, EIO2 Set-up Time EIO1, EIO2 Hold Time Symbol fCP tW1 tW2 tr, tf tDSU tDHD tCL1 tCL2 tLC1 tLC2 tPHL tESU tEHD CL=15 pF -- -- Condition DUTY=50%, VDD=4.5 V -- -- -- -- -- -- -- -- -- Min. -- 56 70 -- 50 40 0 65 65 65 -- 50 50 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 6.5 -- -- 20 -- -- -- -- -- -- 236 -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns
Note: The above values are quaranteed when TCP is protected from light.
tf tW1 CP 0.8 VDD 0.8 VDD 0.2 VDD tDSU D0~D3 0.8 VDD 0.2 VDD tCL1 LOAD 0.2 VDD tW2 tr tf tLC2 tCL2 0.8 VDD 0.8 VDD 0.2 VDD tLC1 tDHD tW1 tr tW1 0.8 VDD 0.2 VDD 0.8 VDD
0.8 VDD CP 1 LOAD tPHL EIO1, EIO2 (Output) 0.2 VDD EIO1, EIO2 (Input) 0.2 VDD tESU tEHD 0.2 VDD 2 38 0.2 VDD 39 40 0.2 VDD 41
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FUNCTIONAL DESCRIPTION
Pin Descriptions VDD, VSS Power supply for the device. VDD is set to 2.7 V to 5.5 V. VSS is set to 0 V. V1L, V1R, V3L, V3R, V4L, V4R, VEEL, VEER Bias power supply for the LCD drive voltages. Power supply should be VDDV1>V3>V4>VEE. DISPOFF Input for controlling the output level of O1 to O160. The V1 level is output from O1 to O160 pins during "L" level input. Refer to Truth Table. DF Input for LCD drive wave form AC synchronization. O1~O160 LCD drive outputs that correspond to each bit of the latch (II). Depending on the combination of the contents of the latch (display data) and DF signal, one of 4 levels (V1, V3, V4, VEE) is output. Refer to Truth Table. CP Clock pulse input for display data reading. Data is taken into the latch (I) at the falling edge of the clock pulse. Use an even number for the clock number per line (the number of the clock pulses during the period from Load input to the next Load input). EIO1, EIO2 Chip Select Signal Input/Output. Input/Output are controlled by the SHL input. If the SHL input at "L"level,EIO1 is output and EIO2 is input. If the SHL input is at "H" level,EIO1 is input and EIO2 is output. If the SHL is at "L" level, the first EIO2 is fixed to "L"level,and the following EIO2 is connected to the preceding EIO1. If the SHL is at "H"level,the first EIO1 is fixed to "L" level, and the following EIO1 is connected to the preceding EIO2 as shown below.
When SHL is at "L" level Start data O160 EIO2 EIO1 EIO2 EIO1 EIO2 End data O1
When SHL is at "H" level End data O160 EIO1 EIO2 EIO1 EIO2 Start data O1 EIO1
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D0, D1, D2, D3 These are display data inputs that input data with clock synchronization. The table below shows the relationship between the LCD output for the display data and DFs and the LCD.
Display Data L H L H DF L L H H LCD drive output Non-selection level (V3) Selection level (V1) Non-selection level (V4) Selection level (VEE) LCD OFF ON OFF ON
LOAD This is an input to simultaneously output the display data of one line stored in the latch (I). At the falling edge, the data in the latch (I) is transferred to the latch (II) end is output. SHL Input to select for display data reading direction. Input of "L" level at Vss level fetches data in the direction from O160 to O1 sequentially, while input of "H" level at VDD fetches data in the direction from O1 to O160. The table below shows the relationship between read data and driver outputs (O1 to O160).
SHL EIO1 EIO2 Numbers of the clock pulse Data input 40 clocks 39 clocks 38 clocks ... 3 clocks 2 clocks ... D0 O1 O5 O9 O153 O149 ... D1 O2 O6 O10 O154 O150 D2 D3 D0 H Inputs Outputs D1 D2 D3 O3 O4 O160 O159 O158 O157 O7 O8 O156 O155 O154 O153 O11 O12 O152 O151 O150 O149 ... ... ... ... ... ... O151 O152 O12 O11 O10 O9 O155 O156 O8 O7 O6 O5
1 clocks O157 O158 O159 O160 O4 O3 O2 O1
L
Outputs Inputs
TRUTH TABLE
DF L L H H X
X : don't care
Display Data L H L H X
DISPOFF H H H H L
Driver output (01~0160) V3 V1 V4 VEE V1
NOTES ON USAGE (when turning the power ON or OFF) If a high voltage is applied to a LCD drive system while the logic supply is floating, over-current may destroy the device, because the voltage over the LCD drive system is high. Follow the sequence below when turning the power ON or OFF. Power ON : Logic system ON AE LCD drive system ON, or both ON Power OFF : LCD drive system OFF AE logic system OFF, or both OFF 9/9

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